1 file number 1573.4 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999 IRF510 5.6a, 100v, 0.540 ohm, n-channel power mosfet this n-channel enhancement mode silicon gate power ?ld effect transistor is an advanced power mosfet designed, tested, and guaranteed to withstand a speci?d level of energy in the breakdown avalanche mode of operation. all of these power mosfets are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta17441. features 5.6a, 100v ? ds(on) = 0.540 ? single pulse avalanche energy rated soa is power dissipation limited nanosecond switching speeds linear transfer characteristics high input impedance related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging jedec to-220ab ordering information part number package brand IRF510 to-220ab IRF510 note: when ordering, include the entire part number. d g s source drain (flange) drain gate data sheet november 1999
2 absolute maximum ratings t c = 25 o c, unless otherwise speci?d IRF510 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v ds 100 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 100 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 5.6 a t c = 100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 4a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 20 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d 43 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29 w/ o c single pulse avalanche energy rating (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e as 19 mj operating and storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j ,t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss v gs = 0v, i d = 250 a, (figure 10) 100 - - v gate to threshold voltage v gs(th) v gs = v ds , i d = 250 a 2.0 - 4.0 v zero-gate voltage drain current i dss v ds = 95v, v gs = 0v - - 25 a v ds = 0.8 x rated bv dss , v gs = 0v, t j = 150 o c - - 250 a on-state drain current (note 2) i d(on) v ds > i d(on) x r ds(on)max , v gs = 10v (figure 7) 5.6 - - a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) v gs = 10v, i d = 3.4a (figures 8, 9) - 0.4 0.54 ? forward transconductance (note 2) g fs v gs = 50v, i d = 3.4a (figure 12) 1.3 2.0 - s turn-on delay time t d(on) i d 5.6a, r gs = 24 ? , v dd = 50v, r l = 9 ? , v dd = 50v, v gs = 10v mosfet switching times are essentially independent of operating temperature - 8 12 ns rise time t r -2563ns turn-off delay time t d(off) -157 ns fall time t f -1259ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 10v, i d = 5.6a, v ds = 0.8 x rated bv dss , i g(ref) = 1.5ma (figure 14) gate charge is essentially independent of operating temperature. - 5.0 30 nc gate to source charge q gs - 2.0 - nc gate to drain ?iller?charge q gd - 3.0 - nc input capacitance c iss v gs = 0v, v ds = 25v, f = 1.0mhz (figure 11) - 135 - pf output capacitance c oss -80 - pf reverse-transfer capacitance c rss -20 - pf internal drain inductance l d measured from the contact screw on tab to center of die modified mosfet symbol showing the internal devices inductances - 3.5 - nh measured from the drain lead, 6mm (0.25in) from package to center of die - 4.5 - nh internal source inductance l s measured from the source lead, 6mm (0.25in) from header to source bonding pad - 7.5 - nh junction to case r jc - - 3.5 o c/w junction to ambient r ja free air operation - - 80 o c/w l d l s d s g IRF510
3 source to drain diode speci?ations parameter symbol test conditions min typ max units continuous source to drain current i sd modified mosfet symbol showing the integral reverse p-n junction diode - - 5.6 a pulse source to drain current (note 3) i sdm - - 20 a source to drain diode voltage (note 2) v sd t j = 25 o c, i sd = 5.6a, v gs = 0v (figure 13) - - 2.5 v reverse recovery time t rr t j = 25 o c, i sd = 5.6a, di sd /d t = 100a/ s 4.6 96 200 ns reverse recovered charge q rr t j = 25 o c, i sd = 5.6a, di sd /d t = 100a/ s 0.17 0.4 0.83 c notes: 2. pulse test: pulse width 300 s, duty cycle 2%. 3. repetitive rating: pulse width limited by max junction temperature. see transient thermal impedance curve (figure 3). 4. v dd = 25v, start t j = 25 o c, l = 910 h, r g = 25 ? , peak i as = 5.6a. typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. maximum transient thermal impedance d s g t c , case temperature ( o c) 25 50 75 100 125 150 175 0 power dissipation multiplier 0 0 0.2 0.4 0.6 0.8 1.0 1.2 t c , case temperature ( o c) 50 75 100 150 25 175 10 8 6 0 4 i d, drain current (a) 2 125 z jc , transient 10 1 0.1 0.01 10 -2 10 -5 10 -4 10 -3 0.1 1 10 single pulse t 1 , rectangular pulse duration (s) duty factor: d = t 1 /t 2 peak t j = p dm x z jc + t c t 2 p dm t 1 notes: thermal impedance ( o c/w) 0.01 0.02 0.5 0.2 0.1 0.05 IRF510
4 figure 4. forward bias safe operating area figure 5. output characteristics figure 6. saturation characteristics figure 7. transfer characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature typical performance curves unless otherwise speci?d (continued) 100 10 1 10 3 110 10 2 0.1 i d , drain current (a) v ds , drain to source voltage (v) operation in this region is limited by r ds(on) t c = 25 o c 10 s 100 s 1ms t j = 175 o c single pulse v ds , drain to source voltage (v) 10 20 30 40 050 10 8 6 0 4 i d , drain current (a) v gs = 10v v gs = 8v v gs = 7v v gs = 6v v gs = 5v v gs = 4v pulse duration = 80 s 2 duty cycle = 0.5% max v ds, drain to source voltage (v) 2468 010 10 8 6 0 4 i d , drain current (a) v gs = 10v v gs = 8v v gs = 7v v gs = 6v v gs = 5v v gs = 4v pulse duration = 80 s 2 duty cycle = 0.5% max v ds 50v pulse duration = 80 s t j = 175 o c t j = 25 o c i d(on) , on-state drain current (a) v gs , gate to source voltage (v) 10 1 0.1 10 -2 0 246 810 duty cycle = 0.5% max i d, drain current (a) 4 8 12 16 020 5 4 3 0 2 r ds(on) , drain to source v gs = 20v pulse duration = 80 s 1 v gs = 10v on resistance ( ? ) duty cycle = 0.5% max 3.0 1.8 0.6 0 60 160 180 -60 t j , junction temperature ( o c) normalized on resistance i d = 3.4a, v gs = 10v 2.4 1.2 0 -40 -20 20 40 80 100 140 120 pulse duration = 80 s duty cycle = 0.5% max IRF510
5 figure 10. normalized drain to source breakdown voltage vs junction temperature figure 11. capacitance vs drain to source voltage figure 12. transconductance vs drain current figure 13. source to drain diode voltage figure 14. gate to source voltage vs gate charge typical performance curves unless otherwise speci?d (continued) 1.25 1.05 0.85 0 60 160 180 -60 t j , junction temperature ( o c) normalized drain to source i d = 250 a 1.15 0.95 0.75 -40 -20 20 40 80 100 140 120 breakdown voltage v ds , drain to source voltage (v) c, capacitance (pf) 500 400 300 200 100 0 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd c iss c oss c rss 12 5102 5 10 2 i d, drain current (a) 2468 010 2.5 2.0 1.5 0 1.0 g fs , transconductance (s) pulse duration = 80 s 0.5 v ds 50v t j = 175 o c t j = 25 o c duty cycle = 0.5% max t j = 175 o c t j = 25 o c i sd , source to drain current (a) v sd , source to drain voltage (v) 100 10 1 0.1 0 0.4 0.8 1.2 1.6 2.0 pulse duration = 80 s duty cycle = 0.5% max q g , gate charge (nc) 2468 010 20 16 12 0 8 v gs, gate to source voltage (v) v ds = 80v 4 v ds = 50v v ds = 20v i d = 3.4a IRF510
6 test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. switching time test circuit figure 18. resistive switching waveforms figure 19. gate charge test circuit figure 20. gate charge waveform t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 0.3 f 12v battery 50k ? v ds s dut d g i g(ref) 0 (isolated v ds 0.2 f current regulator i d current sampling i g current sampling supply) resistor resistor same type as dut q g(tot) q gd q gs v ds 0 v gs v dd i g(ref) 0 IRF510
7 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 IRF510
|
